make Command

Purpose

Maintains, updates, and regenerates groups of programs.

Syntax

make [ -DVariable ] [ -d Option ] [ -e ] [ -i ] [ -j[Jobs]] [ -k ] [ -n ] [ -p ] [ -q ] [ -r ] [ -S ] [ -s ] [ -t ] [ -f MakeFile ... ] [ Target ... ]

Description

The make command assists you in maintaining a set of programs. Input to the make command is a list of file dependency specifications.

There are four types of lines in a makefile: file dependency specifications, shell commands, variable assignments, and comments. In general, lines can be continued from one line to the next by ending them with a \ (backslash). The trailing newline character and initial white space on the following line are compressed into a single space.

File Dependency Specifications

Dependency lines consist of one or more targets, an operator, and zero or more prerequisites (sources). This creates a relationship where the targets depend on the prerequisites and are usually created from them. The exact relationship between the target and the prerequisite is determined by the operator that separates them. The operators are as follows:

File dependency specifications have two types of rules, inference and target. Inference rules specify how a target is to be made up-to-date. These rules have one target with no / (slash) and a minimum of one . (period). Target rules specify how to build the target. These rules can have more than one target.

Makefile Execution

The make command executes the commands in the makefile line by line. As make executes each command, it writes the command to standard output (unless otherwise directed, for example, using the -s flag). A makefile must have a Tab in front of the commands on each line.

Target Rules

Target rules have the following format:

target[target...] : [prerequisite...] [;command]
<Tab>command

Special Targets

Special targets cannot be included with other targets; that is, they must be the only target specified. These targets control the operation of the make command. These targets are:

Inference Rules

The make command has a default set of inference rules, which you can supplement or overwrite with additional inference rules definitions in the makefile. The default rules are stored in the external file, /usr/ccs/lib/aix.mk. You can substitute your own rules file by setting the MAKERULES variable to your own file name from the command line. The following line shows how to change the rules file from the command line:

make MAKERULES=/pathname/filename

Inference rules consist of target suffixes and commands. From the suffixes, the make command determines the prerequisites, and from both the suffixes and their prerequisites, the make command determines how to make a target up-to-date. Inference rules have the following format:

rule:
<Tab>command
...

where rule has one of the following forms:

The .s1 and .s2 suffixes are defined as prerequisites of the special target, .SUFFIXES. The suffixes .s1 and .s2 must be known suffixes at the time the inference rule is displayed in the makefile. The inference rules use the suffixes in the order in which they are specified in .SUFFIXES. A new inference rule is started when a new line does not begin with a <Tab> or # character.

If rule is empty, for example:

rule: ;

execution has no effect, and the make command recognizes that the suffix exists, but takes no actions when targets are out-of-date.

A ~ (tilde) in the preceding rules refers to an SCCS file. Therefore, the rule, .c~.o, would transform an SCCS C language prerequisite file into an object file (.o). Because the s. of the SCCS file is a prefix, it is incompatible with the make command's suffix view. The ~ (tilde) is a way of changing any file reference into an SCCS file reference.

Libraries

A target or prerequisite can also be a member of an archive library and is treated as such if there are parentheses in the name. For example, library(name) indicates that name is a member of the archive library library. To update a member of a library from a particular file, you can use the format .s1.a, where a file with the .s1 suffix is used to update a member of the archive library. The .a refers to an archive library.

Using Macros

In makefiles, macro definitions are defined in the format:

variable=value

Macros can be displayed throughout the makefile, as follows:

• If a macro is displayed in a target line, it is evaluated when the target line is read.
• If a macro is displayed in a command line, it is evaluated when the command is executed.
• If a macro is displayed in a macro definition line, it is evaluated when the new macro is displayed in a rule or command.

If a macro has no definition, it defaults to NULL. A new macro definition overwrites an existing macro of the same name. Macros assignments can come from the following, in the listed order:

1. Default inference rules
2. Contents of the environment
3. Makefiles
4. Command lines.
   Note: The -e flag causes environment variables to override those defined in the makefile.

Shell Commands

Each target can have associated with it a series of shell commands, usually used to create the target. Each of the commands in this script must be preceded by a Tab. While any target can be displayed on a dependency line, only one of these dependencies can be followed by a creation script, unless the :: operator is used.

If the first, or first two characters, of the command line are one or all of @ (at sign), - (hyphen), and + (plus sign), the command is treated specially, as follows:

A command that has no metacharacters is directly executed by the make command. For example, the make command consigns the first command in the following example to the shell because it contains the > (greater than sign) shell metacharacter. The second command in the following example does not contain any shell metacharacters, so the make command executes it directly:

target: dependency
        cat dependency > target
        chmod a+x target

Bypassing the shell saves time, but it can cause problems. For example, attempting to execute a C shell script from within a makefile by setting the SHELL macro to /bin/csh will not work unless the command line also contains at least one shell metacharacter.

SHELL=/bin/csh
   
target: dependency
        my_csh_script

This makefile fails because the make command attempts to run my_csh_script instead of consigning it to the C shell.

Variable Assignments

Variables in the make command are much like variables in the shell and consist of all uppercase letters. The = operator assigns values to variables. Any previous variable is then overridden. Any white space before the assigned value is removed.

macro += word ... 
macro += macro1 

The += operator when used in place of = appends the new value with a single space is inserted between the previous contents of the variable and the appended value.

Variables are expended by surrounding the variable name with either { } (braces) or ( ) (parentheses) and preceding it with a $ (dollar sign). If the variable name contains only a single letter, the surrounding braces or parentheses are not required. This shorter form is not recommended.

Variable substitution occurs at two distinct times, depending on where the variable is being used. Variables in dependency lines are expanded as the line is read. Variables in shell commands are expanded when the shell command is executed.

The four classes of variables (in order of increasing precedence) are:

VPATH=src:/usr/local/src

Flags

Exit Status

When the -q flag is specified, this command returns the following exit values:

Otherwise, this command returns the following exit values:

Examples

1. To make the first target found in the makefile, type:

   make

2. To display, but not run, the commands that the make command would use to make a file:

   make  -n search.o

   Doing this will verify that a new description file is correct before using it.
3. To create a makefile that says that pgm depends on two files, a.o and b.o, and that they, in turn, depend on their corresponding prerequisite files (a.c and b.c) and a common file, incl.h, type:

   pgm: a.o b.o
             c89 a.o b.o -o pgm
   a.o: incl.h a.c
             c89 -c a.c
   b.o: incl.h b.c
             c89 -c b.c

4. To make optimized .o files from .c files, type:

   .c.o:
             c89 -c -o $*.c
   or:
   .c.o:
             c89 -c -o $<

5. To view the contents of the built-in rules, type:

   make  -p  -f /dev/null 2>/dev/null

6. To use the make command in parallel mode with a maximum of 10 parallel jobs to be used for building the target specified in the makefile, type:

   make -j10

Files